Turbo-product codes (TPC) are being explored for use in next generation solid state storage systems. Although current TPC techniques have a number of attractive features, one downside of current TPC techniques is the associated error floor. At high signal to noise (SNR) ratios, the page failure rate (PFR) with current TPC techniques flattens out. To put it another way, when the bit error rate (BER) is low, performance is relatively flat. In contrast, error correction codes used in current solid state storage solutions have a waterfall-like performance curve in the high SNR (i.e., low BER) region so that there is no leveling-off of performance. New TPC techniques which push down the error floor (e.g., so that the PFR at which the performance curve levels out is better than before) would be desirable.